731 lines
19 KiB
C++
731 lines
19 KiB
C++
// This may look like C code, but it is really -*- C++ -*-
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// ------------------------------------------------------------------
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// The Goldware Library
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// Copyright (C) 1990-1999 Odinn Sorensen
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// Copyright (C) 1999-2000 Alexander S. Aganichev
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// ------------------------------------------------------------------
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Library General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Library General Public License for more details.
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//
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// You should have received a copy of the GNU Library General Public
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// License along with this program; if not, write to the Free
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// Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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// MA 02111-1307, USA
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// ------------------------------------------------------------------
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// $Id$
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// ------------------------------------------------------------------
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// Get operating system version.
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// ------------------------------------------------------------------
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#include <cstdio>
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#include <gstrall.h>
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#include <gutlmisc.h>
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#if defined(__WIN32__)
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#include <windows.h>
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#elif defined(__GNUC__)
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#include <sys/utsname.h>
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#endif
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#if defined(__BEOS__)
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#include <File.h>
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#include <AppFileInfo.h>
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#endif
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// ------------------------------------------------------------------
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#define _MAX_VNAME_LEN 12
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#define _MAX_MNAME_LEN 30
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// ------------------------------------------------------------------
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inline static bool HaveCPUID()
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{
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// TO_PORT_TAG: CPUID
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#if defined(_MSC_VER)
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__try
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{
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__asm
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{
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xor eax, eax
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cpuid
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}
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}
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__except(EXCEPTION_EXECUTE_HANDLER)
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{
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return false;
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}
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return true;
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#elif defined(__GNUC__)
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return true;
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#else
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return false;
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#endif
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}
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// ------------------------------------------------------------------
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static void cpuname(int family, int model, const char *v_name, char *m_name)
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{
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if (!strcmp("AuthenticAMD", v_name))
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{
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switch (family)
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{
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case 4:
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switch (model)
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{
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case 3:
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case 7:
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strcpy(m_name, "AMD486DX2");
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break;
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case 8:
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case 9:
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strcpy(m_name, "AMD486DX4");
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break;
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case 14:
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case 15:
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strcpy(m_name, "AMD5x86");
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break;
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default:
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sprintf(m_name, "AMD486_M%d", model);
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}
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break;
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case 5:
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switch (model)
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{
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case 0:
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case 1:
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case 2:
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case 3:
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strcpy(m_name, "AMD_K5");
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break;
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case 6:
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case 7:
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strcpy(m_name, "AMD_K6");
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break;
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case 8:
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strcpy(m_name, "AMD_K6-2");
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break;
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case 9:
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case 10:
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case 11:
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case 12:
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strcpy(m_name, "AMD_K6-3");
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break;
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case 13:
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case 14:
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case 15:
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strcpy(m_name, "AMD_K6-3+");
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break;
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default:
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sprintf(m_name, "AMD_F%dM%d", family, model);
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}
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break;
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case 6:
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switch (model)
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{
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case 1:
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case 2:
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case 4:
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strcpy(m_name, "AMD_Athlon");
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break;
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case 3:
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strcpy(m_name, "AMD_Duron");
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break;
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default:
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sprintf(m_name, "AMD_K7_M%u", model);
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}
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break;
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case 15:
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strcpy(m_name, "AMD64");
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break;
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default:
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sprintf(m_name, "AMD_F%dM%d", family, model);
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}
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}
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else if (!strcmp("GenuineIntel", v_name))
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{
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switch (family)
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{
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case 4:
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switch (model)
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{
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case 0:
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case 1:
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strcpy(m_name, "i486DX");
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break;
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case 2:
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strcpy(m_name, "i486SX");
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break;
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case 3:
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strcpy(m_name, "i486DX2");
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break;
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case 4:
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strcpy(m_name, "i486SL");
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break;
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case 5:
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strcpy(m_name, "i486SX2O");
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break;
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case 7:
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strcpy(m_name, "i486DX2E");
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break;
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case 8:
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strcpy(m_name, "i486DX4");
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break;
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default:
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sprintf(m_name, "i486_M%d", model);
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}
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break;
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case 5:
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switch (model)
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{
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case 1:
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strcpy(m_name, "iP");
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break;
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case 2:
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strcpy(m_name, "iP54C");
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break;
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case 3:
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strcpy(m_name, "iP_OverDrive");
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break;
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case 4:
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strcpy(m_name, "iP55C");
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break;
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default:
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sprintf(m_name, "iF%dM%d", family, model);
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}
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break;
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case 6:
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switch (model)
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{
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case 1:
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strcpy(m_name, "iP-Pro");
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break;
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case 3:
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case 5:
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strcpy(m_name, "iP-II");
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break;
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case 6:
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strcpy(m_name, "iCeleron");
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break;
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case 7:
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case 8:
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case 11:
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strcpy(m_name, "iP-III");
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break;
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case 13:
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strcpy(m_name, "iP-M"); // Pentium M "Centrino" (Pentium Mobile)
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break;
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default:
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sprintf(m_name, "iF%dM%d", family, model);
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}
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break;
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case 15:
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switch (model)
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{
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/* case 2: // 15-2-7, 15-4-1
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strcpy(m_name, "iXeon");
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break;
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*/
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default:
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strcpy(m_name, "iP-IV");
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break;
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}
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break;
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default:
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sprintf(m_name, "iF%dM%d", family, model);
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}
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}
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else if (!strcmp("GenuineTMx86", v_name))
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{
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switch (family)
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{
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case 15:
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switch(model){
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case 2: // Transmeta Efficeon(tm) Processor TM8000
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sprintf(m_name, "TM8000");
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break;
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default:
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sprintf(m_name, "TM F%dM%d", family, model);
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}
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break;
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default:
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sprintf(m_name, "TM F%dM%d", family, model);
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}
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}
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else if (!strcmp("CyrixInstead", v_name))
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sprintf(m_name, "CyrF%dM%d", family, model);
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else if (!strcmp("CentaurHauls", v_name))
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{
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switch (family)
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{
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case 6: // VIA C3 Nehemiah = F6M9; VIA C3 Samuel 2 = F6M7
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sprintf(m_name, "VIA_C3");
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break;
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default:
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sprintf(m_name, "VIA F%dM%d", family, model);
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}
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}
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else
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{
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if (model) {
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sprintf(m_name, "CPU %3s-F%dM%d", v_name, family, model);
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}else{
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switch (family)
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{
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case 0:
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sprintf(m_name, "CPU %s", v_name);
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break;
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case 3:
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case 4:
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sprintf(m_name, "%s-%u86", v_name, family);
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break;
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default:
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sprintf(m_name, "CPU %3s-F%dM%d", v_name, family, model);
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}
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}
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}
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}
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// ------------------------------------------------------------------
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char *gcpuid(char *_cpuname)
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{
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static struct scpuid_t{
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dword cpu; /* x86, where x=cpu */
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dword cpu_high; /* highest CPUID capability */
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#if defined(_MSC_VER)
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union
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{
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char vendor[_MAX_VNAME_LEN+1];
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struct
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{
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dword dw0;
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dword dw1;
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dword dw2;
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} dw;
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};
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#else
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char vendor[3*sizeof(dword)+1]; /* CPU vendor string 12 bytes, 13th byte is zero */
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#endif
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uint8_t family; /* CPU stepping number, 4 bits */
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uint8_t model; /* CPU model number, 4 bits */
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uint8_t stepping; /* CPU stepping value, 4 bits */
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// unsigned cpu_id; /* stepping ID, 12 bits: 0x0FMS */
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// unsigned features; /* CPU features info */
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}scpuid; /* ISO C: static variabled is initialised with 0 */
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#if defined(_MSC_VER)
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#undef and // and is defined as &&, this is conflicted with assembler instruction "and"
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__asm
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{
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// get the vendor string
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xor eax, eax
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cpuid
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// mov scpuid.cpu_high, eax
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mov scpuid.dw.dw0, ebx
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mov scpuid.dw.dw1, edx
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mov scpuid.dw.dw2, ecx
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// get the CPU family, model, stepping, features bits
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mov eax, 1
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cpuid
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// mov scpuid.features, edx
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mov bx, ax
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and ax, 0x0F0F // 3855 // 0x0F0F
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mov scpuid.stepping, al
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mov scpuid.family, ah
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shr bl, 4
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mov scpuid.model,bl
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}
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#define and &&
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cpuname( scpuid.family, scpuid.model, scpuid.vendor, _cpuname);
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#elif defined(__GNUC__) && defined(__i386__)
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asm( /* assembler code is based on code of FreeBSD kernel sources */
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/* uses AT&T assembler notation */
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/* Step 1. Try to toggle alignment check flag; does not exist on 386. */
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"pushfl\n\t"
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"popl %%eax\n\t"
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"movl %%eax,%%ecx\n\t"
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"orl $0x00040000,%%eax\n\t" /* sets a alignment check flag */
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"pushl %%eax\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %%eax\n\t"
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"xorl %%ecx,%%eax\n\t"
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"andl $0x00040000,%%eax\n\t" /* test alignment check flag */
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"pushl %%ecx\n\t"
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"popfl\n\t"
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"testl %%eax,%%eax\n\t" /* alignment check flag is set? */
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"jnz try486\n\t"
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/* NexGen CPU does not have aligment check flag. */
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"pushfl\n\t"
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"movl $0x5555, %%eax\n\t"
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"xorl %%edx, %%edx\n\t"
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"movl $2, %%ecx\n\t"
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"clc\n\t"
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"divl %%ecx\n\t"
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"jz nexgen\n\t"
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"popfl\n\t"
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"movl $3,%0\n\t" /* CPU 386 */
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"jmp end\n"
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"nexgen:"
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"popfl\n\t"
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"movl $5,%0\n\t" /* CPU NX586 */
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"movl $0x4778654e,%1\n\t" /* store vendor string */
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"movl $0x72446e65,%1+4\n\t" /* "NexGenDriven" */
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"movl $0x6e657669,%1+8\n\t"
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// "movl $0,%1+12\n\t" // vendor is zero-filled already
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"jmp end\n"
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/* Step2. Try to toggle identification flag; does not exist on early 486s.*/
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"try486:"
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"pushfl\n\t"
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"popl %%eax\n\t"
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"movl %%eax,%%ecx\n\t"
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"xorl $0x00200000,%%eax\n\t" /* sets a identification bit */
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"pushl %%eax\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %%eax\n\t"
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"xorl %%ecx,%%eax\n\t"
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"andl $0x00200000,%%eax\n\t" /* test identification bit */
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"pushl %%ecx\n\t"
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"popfl\n\t"
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"testl %%eax,%%eax\n\t" /* if identification flag is set then cpuid CPU's command may be used */
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"jnz trycpuid\n\t"
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"movl $4,%0\n\t" /* CPU 486 */
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/*
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* Check Cyrix CPU
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* Cyrix CPUs do not change the undefined flags following
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* execution of the divide instruction which divides 5 by 2.
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*
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* Note: CPUID is enabled on M2, so it passes another way.
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*/
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"pushfl\n\t"
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"movl $0x5555, %%eax\n\t"
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"xorl %%edx, %%edx\n\t"
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"movl $2, %%ecx\n\t"
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"clc\n\t"
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"divl %%ecx\n\t"
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"jnc trycyrix\n\t"
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"popfl\n\t"
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"jmp end\n" /* You may use Intel CPU */
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"trycyrix:"
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"popfl\n\t"
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/*
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* IBM Bluelighting CPU also doesn't change the undefined flags.
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* Because IBM doesn't disclose the information for Bluelighting
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* CPU, we couldn't distinguish it from Cyrix's (including IBM
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* brand of Cyrix CPUs).
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*/
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"movl $0x69727943,%1\n\t" /* store vendor string */
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"movl $0x736e4978,%1+4\n\t" /* "CyrixInstead" */
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"movl $0x64616574,%1+8\n\t"
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"jmp end\n"
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|
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/* Step 3. Use the `cpuid' instruction. */
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"trycpuid:"
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"xorl %%eax,%%eax\n\t"
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".byte 0x0f,0xa2\n\t" /* cpuid 0 */
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"movl %%eax,%2\n\t" /* "cpuid 1" capability */
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"movl %%ebx,%1\n\t" /* store vendor string */
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"movl %%edx,%1+4\n\t"
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"movl %%ecx,%1+8\n\t"
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// "movb $0,%1+12\n\t" // vendor is zero-filled already
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"andl %%eax,%%eax\n\t" /* "cpuid 1" is allowed? (eax==1?) */
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"jz i586\n\t" /* no, skip "cpuid 1" */
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|
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"movl $1,%%eax\n\t"
|
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".byte 0x0f,0xa2\n\t" // cpuid 1
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// "movl %%eax,%6\n\t" // store cpu_id
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// "movl %%edx,%7\n\t" // store cpu_feature
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|
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"movb %%al,%%bl\n\t"
|
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"shrb $4,%%bl\n\t" // extract CPU model
|
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"movb %%bl,%4\n\t" // store model
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|
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"andl $0x0F0F,%%eax\n\t" // extract CPU family type and stepping
|
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"movb %%al,%5\n\t" // store stepping
|
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"movb %%ah,%3\n\t" // store family
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"cmpb $5,%%ah\n\t"
|
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"jae i586\n\t"
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|
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/* less than Pentium; must be 486 */
|
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"movl $4,%0\n\t" /* CPU 486 */
|
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"jmp end\n"
|
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"i586:\n\t" /* Pentium and greater. Store family type into CPU type var */
|
|
"movb %%ah,%0\n"
|
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"end:\n\t"
|
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"nop\n\t"
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|
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: /* output */
|
|
"=m" (scpuid.cpu) /* %0 */
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,"=m" (scpuid.vendor) /* %1 */
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,"=m" (scpuid.cpu_high) /* %2 */
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,"=m" (scpuid.family) /* %3 */
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,"=m" (scpuid.model) /* %4 */
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,"=m" (scpuid.stepping) /* %5 */
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// ,"=m" (scpuid.cpu_id) /* %6 */
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// ,"=m" (scpuid.features) /* %7 */
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: /* no input */
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: /* modified registers */
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"eax", "ebx", "ecx", "edx", "esp"
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);
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cpuname(scpuid.family?scpuid.family:scpuid.cpu, scpuid.model, scpuid.vendor, _cpuname);
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|
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#else
|
|
#if defined(MSDOS) || defined(DOS) || defined(__MSDOS__) || defined(_DOS) \
|
|
|| defined(WIN32) || defined(__WIN32__) || defined(_WIN) || defined(WINNT) \
|
|
|| defined(__OS2__) || defined(OS2)
|
|
cpuname(0, 0, "x86", _cpuname);
|
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#else
|
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cpuname(0, 0, "UNKNOWN", _cpuname);
|
|
#endif
|
|
#endif
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|
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return _cpuname;
|
|
}
|
|
|
|
|
|
// ------------------------------------------------------------------
|
|
|
|
char* ggetosstring(void) {
|
|
|
|
static char osstring[256] = "";
|
|
|
|
if(*osstring == NUL) {
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|
|
|
char processor[_MAX_MNAME_LEN] = "";
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|
|
|
#if defined(__UNIX__) || defined(__DJGPP__) || defined(__EMX__)
|
|
|
|
struct utsname info;
|
|
|
|
gcpuid(processor);
|
|
|
|
if(uname(&info) != -1) {
|
|
if(!processor[0])
|
|
strcpy(processor,info.machine);
|
|
|
|
#if defined(__EMX__)
|
|
sprintf(osstring, "%s %s.%s %s", info.sysname, info.version, info.release, processor);
|
|
#elif defined(__DJGPP__)
|
|
sprintf(osstring, "%s %s.%s %s", info.sysname, info.release, info.version, processor);
|
|
#elif defined(__BEOS__)
|
|
BAppFileInfo appFileInfo;
|
|
version_info sys_ver = {0};
|
|
BFile file("/boot/beos/system/lib/libbe.so", B_READ_ONLY);
|
|
appFileInfo.SetTo(&file);
|
|
appFileInfo.GetVersionInfo(&sys_ver, B_APP_VERSION_KIND);
|
|
sprintf(osstring, "%s %s %s", info.sysname, sys_ver.short_info, processor);
|
|
#else
|
|
sprintf(osstring, "%s %s %s", info.sysname, info.release, processor);
|
|
#endif
|
|
}
|
|
else
|
|
strcpy(osstring, "unknown");
|
|
|
|
#elif defined (__WIN32__)
|
|
|
|
OSVERSIONINFO info;
|
|
SYSTEM_INFO si;
|
|
char ostype[16];
|
|
|
|
GetSystemInfo(&si);
|
|
info.dwOSVersionInfoSize = sizeof(OSVERSIONINFO);
|
|
if(GetVersionEx(&info)) {
|
|
switch(info.dwPlatformId) {
|
|
case VER_PLATFORM_WIN32_NT:
|
|
strcpy(ostype, "WinNT");
|
|
break;
|
|
case VER_PLATFORM_WIN32_WINDOWS:
|
|
strcpy(ostype, "Win9x");
|
|
break;
|
|
default:
|
|
strcpy(ostype, "Win32s");
|
|
break;
|
|
}
|
|
switch(*((WORD*)&si)) {
|
|
case PROCESSOR_ARCHITECTURE_INTEL:
|
|
{
|
|
if (HaveCPUID())
|
|
{
|
|
gcpuid(processor);
|
|
}
|
|
else
|
|
{
|
|
int cpu;
|
|
if( (info.dwPlatformId == VER_PLATFORM_WIN32_NT &&
|
|
info.dwMajorVersion > 3)
|
|
#ifdef VER_PLATFORM_WIN32_CE
|
|
|| info.dwPlatformId == VER_PLATFORM_WIN32_CE
|
|
#endif
|
|
)
|
|
cpu = si.wProcessorLevel;
|
|
else {
|
|
switch(si.dwProcessorType) { /* Windows NT 3.5 and earlier */
|
|
case PROCESSOR_INTEL_386:
|
|
cpu = 3;
|
|
break;
|
|
case PROCESSOR_INTEL_486:
|
|
cpu = 4;
|
|
break;
|
|
case PROCESSOR_INTEL_PENTIUM:
|
|
cpu = 5;
|
|
break;
|
|
case 6: /* Pentium Pro or Pentim II */
|
|
cpu = 6;
|
|
case 15: /* Pentium 4 */
|
|
cpu = 8;
|
|
default:
|
|
cpu = 7;
|
|
break;
|
|
}
|
|
}
|
|
switch(cpu) {
|
|
case 15:
|
|
sprintf(processor, "i886");
|
|
break;
|
|
default:
|
|
if( cpu>9 ) cpu= cpu%10+int(cpu/10)+2;
|
|
sprintf(processor, "i%d86", cpu);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case PROCESSOR_ARCHITECTURE_IA64:
|
|
sprintf(processor, "IA64-%d", si.wProcessorLevel);
|
|
break;
|
|
#ifdef PROCESSOR_ARCHITECTURE_AMD64
|
|
case PROCESSOR_ARCHITECTURE_AMD64:
|
|
sprintf(processor, "AMD64-%d", si.wProcessorLevel);
|
|
break;
|
|
#endif
|
|
case PROCESSOR_ARCHITECTURE_MIPS:
|
|
/* si.wProcessorLevel is of the form 00xx, where xx is an 8-bit
|
|
implementation number (bits 8-15 of the PRId register). */
|
|
sprintf(processor, "MIPS R%u000", si.wProcessorLevel);
|
|
break;
|
|
case PROCESSOR_ARCHITECTURE_ALPHA:
|
|
/* si.wProcessorLevel is of the form xxxx, where xxxx is a 16-bit
|
|
processor version number (the low-order 16 bits of a version
|
|
number from the firmware). */
|
|
sprintf(processor, "Alpha%d", si.wProcessorLevel);
|
|
break;
|
|
case PROCESSOR_ARCHITECTURE_ALPHA64:
|
|
sprintf(processor, "Alpha%d", si.wProcessorLevel);
|
|
break;
|
|
case PROCESSOR_ARCHITECTURE_PPC:
|
|
/* si.wProcessorLevel is of the form xxxx, where xxxx is a 16-bit
|
|
processor version number (the high-order 16 bits of the Processor
|
|
Version Register). */
|
|
switch(si.wProcessorLevel) {
|
|
case 1:
|
|
strcpy(processor, "PPC601");
|
|
break;
|
|
case 3:
|
|
strcpy(processor, "PPC603");
|
|
break;
|
|
case 4:
|
|
strcpy(processor, "PPC604");
|
|
break;
|
|
case 6:
|
|
strcpy(processor, "PPC603+");
|
|
break;
|
|
case 9:
|
|
strcpy(processor, "PPC604+");
|
|
break;
|
|
case 20:
|
|
strcpy(processor, "PPC620");
|
|
break;
|
|
default:
|
|
sprintf(processor, "PPC l%u", si.wProcessorLevel);
|
|
break;
|
|
}
|
|
break;
|
|
#ifdef PROCESSOR_ARCHITECTURE_SHX
|
|
case PROCESSOR_ARCHITECTURE_SHX:
|
|
sprintf(processor, "SH-%d", si.wProcessorLevel);
|
|
break;
|
|
#endif
|
|
#ifdef PROCESSOR_ARCHITECTURE_ARM
|
|
case PROCESSOR_ARCHITECTURE_ARM:
|
|
sprintf(processor, "ARM-%d", si.wProcessorLevel);
|
|
break;
|
|
#endif
|
|
default:
|
|
strcpy(processor, "CPU-unknown");
|
|
break;
|
|
}
|
|
if(info.dwPlatformId == VER_PLATFORM_WIN32_WINDOWS)
|
|
info.dwBuildNumber = info.dwBuildNumber & 0x0000ffffl;
|
|
if(info.dwPlatformId == VER_PLATFORM_WIN32_NT and *info.szCSDVersion != NUL) {
|
|
char _tmp[128];
|
|
strcpy(_tmp, info.szCSDVersion);
|
|
strchg(_tmp, ' ', '_');
|
|
strisrep(_tmp, "Service_Pack_", "SP");
|
|
sprintf(osstring, "%s %u.%u.%u-%s %s", ostype, unsigned(info.dwMajorVersion), unsigned(info.dwMinorVersion), unsigned(info.dwBuildNumber), _tmp, processor);
|
|
}
|
|
else
|
|
sprintf(osstring, "%s %u.%u.%u %s", ostype, unsigned(info.dwMajorVersion), unsigned(info.dwMinorVersion), unsigned(info.dwBuildNumber), processor);
|
|
}
|
|
else
|
|
strcpy(osstring, "Win32-unknown");
|
|
|
|
#else
|
|
|
|
#if defined(__MSDOS__)
|
|
const char* osname = "DOS";
|
|
#elif defined(__OS2__)
|
|
const char* osname = "OS/2";
|
|
#endif
|
|
|
|
sprintf(osstring, "%s %d.%02d %s", osname, _osmajor, _osminor, gcpuid(processor));
|
|
|
|
#endif
|
|
}
|
|
|
|
return osstring;
|
|
}
|
|
|
|
|
|
// -------------------------------------------------------------------
|